RISC-V Series

what is going on?

As being a nerd about open source and CPU architecture, I’ve decided to learn more about riscv ISA (Instruction Set Architecture) and try out making a core with it. In past I made my own 8bit ISA and implemented it on FPGA, but it feel now is time to try out bigger 32bits turf and try adding some AI Accelerators as the finishing touch. I have basic knowledge of how CPU works and how to write Verilog, But I feel like I don’t have enough experience in it. I just made a non pipelined CPU before, so this time plan of attack will be different.

plan of attack!?

1. we need to write a software simulator to get to know the waters that we are entering into i.e to understand the ISA better and try to familiarize with it.
2. come up with a good architecture.
3. write the Verilog and test it on Verilator.
4. make an SOC around it.
5. dump it on a FPGA.
6. test with 2 or 3 programs.
7. call it a day.

how much time will it take?

Lots of time to be honest, but I don’t know how much time even approximately it will take. lets say I have deadline goals for every week or so.

what is the real goal here?

To learn new things I don’t know and try to share it with people. it feels like there is a ocean full of things I still don’t know, and its more fun this way. jokes aside the main objective is to understand modern technologies in CPU world and try to implement some of them. at last I should be able to say I built this computer... from scratch!!.

what I want you to do?

Hop on to the train and explore the unknown world….

No, chill and learn things in your own way, but try not to take too much long breaks. try to watch only 8hrs of anime daily, if possible sleep for 10hrs and other time left do what you want.

bye.